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| CY2040-2/3 32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input Features * * * * Precision RTC 32 kHz and 24 MHz output Power-down mode (32 kHz on) is < 50 uA Suspend mode (V24M = off) is typically 5 uA Low RMS period Jitter (< 40 ps) * 16-pin TSSOP package * 3.3V + 5% Voltage Supply * CY2040-2 multiplier 32.000 kHz x 750 = 24.0 MHz (requires a single 32.000 kHz crystal) * CY2040-3 enables the 32 kHz and 24.0 MHz oscillators (requires a 32.768 kHz and 24.000 MHz crystal) Logic Block Diagram XIN32K XOUT32K 32kHz OSC Pin Configuration OUT32K NC 32K P LLE N P D24M # V32K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS O UT24M O UT32KPLL O UT32K XO UT24M X IN 2 4 M VSS NC Q=INPUT DIVIDER PLL V24M POST DIVIDER X IN 3 2 K XO UT32K NC P=FEEDBACK DIVIDER OUT24M XIN24M XOUT24M 24MHz OSC OUT32KPLL PD24M# 32KPLLEN CONTROL LOGIC Cypress Semiconductor Corporation Document #: 38-07122 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 December 14, 2002 CY2040-2/3 Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol NC 32KPLLEN PD24M# V32K[1] V24M[1] XIN32K XOUT32K NC NC VSS Xin24M OUT24M OUT32K OUT32KPLL OUT24M VSS Type NC I, PU I, PU P P I O NC NC P I O O O O P Description No connection (leave it floating). OUT32KPLL (pin 14) output enable (OE). 1 = running, 0 = 3-state. Weak pull-up. Power down pin to turn off OUT32M, OUT32KPLL, PLL, post divider and 24-MHz crystal oscillator. Active Low. 1 = running, 0 = power down. Weak pull-up. 3.3V supply for the 32 kHz oscillator circuit (Vbatt). 3.3V supply for the 24 MHz oscillator and PLL circuits (VDD). Crystal connection input for OSC1. Recommend using CLoad = 6 pF crystal with ESR <= 55 k. Oscillator output pin connected to crystal OSC1. No connection (leave it floating). No connection (leave it floating). Power supply ground. Crystal connection input for OSC2. Recommend to use CLoad = 10pF crystal with ESR <= 20. Can be left floating if 24M crystal is not used (CY2040-2). Oscillator output pin connected to crystal OSC2. Leave this pin unconnected if 24M crystal is not used (CY2040-2). 3.3V 32 kHz buffered output of the reference crystal. 32 kHz output. Can be enabled/disabled by 32KPLLEN pin. 3.3V 24 MHz buffered output: either 32 kHz x 750 (-2) or from 24.0 MHz OSC2 (-3). Power supply ground. Device Configuration Device CY2040-2 CY2040-3 Input Crystals 32.000 kHz crystal with CLoad = 6pF and ESR <= 55 k. Output Frequency OUT32K = 32.000 kHz; OUT24M = 24.000 MHz, OUT32KPLL=32.000kHz 32.768 kHz crystal with CLoad = 6pF and ESR <= 55 k. OUT32K = 32.768 kHz; OUT24M = 24.000 MHz, 24.000 MHz crystal with CLoad = 10pF and ESR <= 20 . OUT32KPLL = 32.768 kHz Note: 1. The two power supply pins, V32K and V24M, should be shorted externally. Document #: 38-07122 Rev. *A Page 2 of 7 CY2040-2/3 Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ................................... -0.5V to +7.0V Input Voltage ...................................... -0.5V to V24M +0.5 Storage Temperature (Non-Condensing) ..............................-55C to +150C Junction Temperature .........................+150C Static Discharge Voltage..................... > 2000V (per MIL-STD-883, Method 3015) Operating Conditions Parameter V32K V24M TA CL Description Vbatt, Supply voltage VDD, Supply voltage Operating Temperature, Ambient Load Capacitance Conditions Relative to VSS Relative to VSS Operating Temperature Range, Ambient Max Capacitive Load on OUT32K, OUT32KPLL, and OUT24M Min. 3.135 3.135 0 Max. 3.465 3.465 70 15 Unit V V C pF tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms DC Characteristics Parameter VIL Description Input low voltage (PD24M# and 32KPLLEN Pins) Input high voltage (PD24M# and 32KPLLEN Pins) Input low current (PD24M# and 32KPLLEN Pins) Input high current (PD24M# and 32KPLLEN Pins) Test Conditions V24M = 3.3 + 5% Min. Typ. Max. 0.2 VDD Unit V VIH V24M = 3.3 + 5% 0.7 VDD V IIL VIN = 0V <1 10 A IIH VIN = V24M <1 5 A IDD Dynamic Supply Current with V24M = V32K = 3.3 + 5%, no load at outputs. fOUT32K = 32.768kHz or 32.000kHz, fOUT24M = 24MHz, fOUT32KPLL = 3-state. Power-down Supply Current V24M = V32K = 3.3 + 5% (PD24M# = "0") 10 25 mA IPT 20 50 A OUT32K (V32K = 3.3V +5%) VOL VOH Output low voltage Output high voltage V32K = 3.3 + 5%, IOL= 8 mA V32K = 3.3 + 5%, IOH= - 8 mA V32K - 0.4 0.4 V OUT24M (V24M = 3.3V +5%) VOL VOH IOZ Output low voltage Output high voltage Output leakage current (OUT24M) V24M = 3.3 + 5%, IOL= 8 mA V24M = 3.3 + 5%, IOH= - 8 mA V24M = 3.3 + 5%, with output disabled V24M - 0.4 1 50 A 0.4 V OUT32KPLL (V24M = 3.3V +5%) VOL VOH Output low voltage Output high voltage V24M = 3.3 + 5%, IOL= 8 mA V24M = 3.3 + 5%, IOH= -8 mA V24M - 0.4 0.4 V Document #: 38-07122 Rev. *A Page 3 of 7 CY2040-2/3 DC Characteristics Parameter IOZ Description Output leakage current (OUT32KPLL) Test Conditions V24M = 3.3 + 5%, with output disabled Min. Typ. 1 Max. 50 Unit A AC Characteristics Parameter tr1 tf1 dc1 tj1 Description OUT32K Rise time OUT32K Fall time OUT32K Duty Cycle Pk-Pk Period jitter Test Conditions 20% to 80% V32K 80% to 20% V32K CLT = 15 pF, measured at V32K/2 32.000 kHz output directly from oscillator (with crystal), measured at V32K/2 V24M = 3.3 + 5%; 20% to 80% V24M V24M = 3.3 + 5%; 80% to 20% V24M V24M = 3.3 + 5%; measured at V24M/2 V24M = V32K = 3.3 + 5%; 32 kHz as input to PLL; measured at V24M/2 V24M = V32K = 3.3 + 5%; 24 MHz output directly from oscillator; measured at V24M/2 V24M = V32K = 3.3 + 5%; 32 kHz as input to PLL; measured at V24M/2 on the 750th output rising edge. V24M = 3.3 + 5%; 20% to 80% V24M V24M = 3.3 + 5%; 80% to 20% V24M V24M = 3.3 + 5%; measured at V24M/2 32.000 kHz output directly from oscillator, measured at V24M/2 From power on (V32K = 3.3 + 5%). Decided by 32.768 kHz/32.000 kHz crystal startup. PD24M# pin high to low (T = OUT24M clock period) From power down mode; PD24M# pin low to high. From power down mode; PD24M# pin low to high. Decided by 24 MHz crystal start-up. T/2 1 6 40 20 40 40 20 Min. Typ. Max. 7.0 7.0 60 40 Unit ns ns % ns OUT32K AC Characteristics OUT24M AC Characteristics tr2 tf2 dc2 tj2 OUT24M Rise Time OUT24M Fall Time OUT24M Duty cycle RMS Period Jitter (CY2040-2, PLL output) RMS Period Jitter (CY2040-3, osc. output) tj3 RMS Long-term Jitter (CY2040-2, PLL output) 4.0 4.0 60 40 40 1.5 ns ns % ps ps ns OUT32KPLL AC Characteristics tr3 tf3 dc3 tj4 OUT32KPLL Rise Time OUT32KPLL Fall Time OUT32KPLL Duty cycle Pk-Pk Period Jitter (32 kHz osc. output) Osc start up time Power down delay time on OUT24M; SYNC Power up time on OUT24M; ASYNC (CY2040-2) Power up time on OUT24M; ASYNC (CY2040-3) 7.0 7.0 60 40 ns ns % ns Other AC Characteristics tstart tPD tPU 3 T+25 5 10 sec ns ms ms Document #: 38-07122 Rev. *A Page 4 of 7 CY2040-2/3 Switching Waveforms Duty Cycle Timing (dc1, dc2, dc3) t1A t1B OUTPUT Output Rise/Fall Time VDD OUTPUT 0V tr tf Power Down and Power up Timing (synchronous modes) VDD POWER DOWN/UP VIL 0V VIH tPU CLKOUT (synchronous) T High Impedance tPD 1/f Crystal Start-up Timing VDD CRYSTAL START-UP CLKOUT 1/f 0V VDD - 10% tstart min. 30us max. 30ms Document #: 38-07122 Rev. *A Page 5 of 7 CY2040-2/3 Application Circuits CY2040-3 CY2040-2 1 NC Note 2 2 32KPLLEN 3 PD24M# 4 V32K Vss 16 1 NC Note 2 Vss 16 out24M 15 Out32KPLL 14 Out32K 13 out24M 15 Out32KPLL 14 Out32K 13 GND 2 32KPLLEN GND Vdd 0.1uF Vdd 24.000MHz Crystal 3 PD24M# 4 V32K 5 V24M 6 Xin32K CY2040-3 Xout24M 12 Xin24M 11 Vss 10 NC 9 0.1uF 5 V24M 6 Xin32K CY2040-2 Xout24M 12 Xin24M 11 Vss 10 NC 9 32.768KHz Crystal 7 Xout32K 8 NC 32.000kHz Crystal 7 Xout32K 8 NC GND GND Note: 2. To disable the OUT32KPLL output, the 32KPLLEN pin should be connected to GND. To enable the OUT32KPLL output, the 32KPLLEN pin should be connected to VDD. Ordering Code CY2040ZC-2 CY2040ZC-3 Package Name Z16 Z16 Package Type 16LD TSSOP 16LD TSSOP Operating Range 0-70C 0-70C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07122 Rev. *A Page 6 of 7 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2040-2/3 Document Title: CY2040-2/3 32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input Document Number: 38-07122 REV. ** *A ECN NO. 109574 121821 Issue Date 01/17/02 12/14/02 Orig. of Change CKN RBI New Data Sheet Power up requirements added to Operating Conditions Information Description of Change Document #: 38-07122 Rev. *A Page 7 of 7 |
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